As demand for low power consumption processors is increasing, reducing dynamic power consumption in switching transistors is gaining interest. One way to reduce dynamic power consumption is by clock gating. The term “clock gating” herein refers to stopping the clock signal from propagating to a logic unit so that the transistors in the logic unit receiving the clock signal do not switch. The term “clock un-gating” herein refers to resuming the clock signal to propagate to a logic unit so that the transistors in the logic unit receiving the clock signal are capable of switching.
Clock signals are distributed in a processor by a grid of tiles of metal wires which are shorted together to provide the same clock signal to all logic units of the processor. FIG. 1 illustrates a snapshot of a clock distribution network 100 with a shorted grid 103 of wires of metal to provide the same clock signal clki at roughly the same time to all points of the shorted grid 103. The clock distribution network 100, in this example, provides the clock signal clki to three functional logic blocks 105, 106, and 107. The clock signal clki is generated by a phase locked loop (PLL) 101 and buffered out to the grid 103 via a spine 102, wherein the spine 102 is a network of buffers and/or inverters to drive the clock signal clki to the grid 103. A logic unit 108 generates an enable signal 109 for all clock drivers 104 that drive the clock signal clki to the grid 103. The enable signal 109 is used for clock gating and un-gating, i.e. to stop and resume clock signal propagation in the functional blocks 105, 106, and 107.
However, clock gating the clock signal clki in the grid 103 of tiles to reduce dynamic power consumption for a particular logic unit (e.g., one of 105, 106, or 107) stops the clock signal clki from propagating to all logic units—all units 105, 106, and 107. Clock gating all logic units 105, 106, and 107 of the processor may shut down the operations of the processor completely.